||Term / Abbr
|Capability Test Board (CTB)
||Capability Test Board (CTB)
||A printed board specifically designed to act as a capability qualifying component (CQC), or to be used by manufacturer to evaluate process variation, provess control, or continuous improvement procedures.
|Ceramic Dual-in-line Package (CERDIP)
||Ceramic Dual-in-line Package (CERDIP)
||A dual in-line-package that has a package body of ceramic material and hermetically sealed by glass. (See also "Dual-in-line Package.")
|Ceramic Pin Grid Aray (CPGA)
||Ceramic Pin Grid Aray (CPGA)
||A pin grid aray package (PGA) made of a ceramic material, hermetically sealed by metal, with leads formed on a grid extending from the bottom of the package.
|Ceramic Quad Flat Pack (CQFP)
||Ceramic Quad Flat Pack (CQFP)
||A quad flad pack (QFP) made of a ceramic material, hermetically sealed by metal, with leads extending grom all four sides.
|Chip Scale Package (CSP)
||Chip Scale Package (CSP)
||See "Fine Pitch BGA/Chip Scale Package"
||An electronic component where a chip is inserted into an opening of a ceramic of glass-epoxy substrate and bonded by wire bonding or TAB techniques. The object of this technique is to reduce the thickness of the COB assembly. The chip may be covered by a resin after bonding.
||A printed board assembly technology that places unpackaged semiconductor dice and interconects them by a wire bonding or similar attachment techniques. Silicon area density is usualy less than that of the printed board.
||Semiconductor chip mounted directly onto flexible printed board.
|Cold Solder Connection
||Cold Solder Connection
||A solder connection that exhibits poor wetting, and that is characterized by a grayish, porous appearance. (This is due to excessive impurities in the solder, inadequate cleaning prior to soldering, and/or the insufficient application of heat during the soldering process.)
||Chip component with dimensions 0.024 in × 0.012 in (imperial); 0.6 mm × 0.3 mm (metric)